1. Field of the Invention
The present invention relates to apparatus for controlling electrical power and, more particularly, to apparatus for controlling electrical power in computer systems and the like.
2. Description of Related Art
Contemporary computer systems frequenty include multiple processors for enhanced speed of operation. Often, for reasons of efficiency and/or economy, such multiple processor computer systems have shared resources, such as memory and I/O subsystems. To ensure that such computer systems work properly, they have been provided with means for ensuring that conflicting accesses to the shared resources are avoided to prevent misreads, errors and the like.
A variety of means have heretofore been developed for preventing conflicting accesses to shared resources in multiple processor systems. One such means which in incorporable into multiple processor systems sharing a bus, has been bus arbitration. Such bus arbitration means have been programmed to prevent conflicting accesses by multiple processors of various shared resources. Another means for accomplishing the same results in system configurations which involve multiple processors and the non-bused resources includes using complex software driven mechanisms. Of course, the use of dedicated resources, wherein each processor can prevent other network processors from accessing their resources, has also been employed in various prior art systems, but such configurations are not able to obtain the benefits of using shared resources, as discussed above.
A critical time for the prevention of conflicting accesses between multiple processors which are sharing resources is during power on reset. If individual processors in such multiple processor systems are not brought up in an orderly fashion, conflicting accesses to shared resources may occur. The need to avoid conflicting accesses is especially pronounced, and especially difficult to deal with, in systems that are reconfigurable to allow either multiple processors or dedicated memory. Final system design is typically not established until late in the manufacturing process of such systems and such design can vary significantly from system, requiring great flexibility and the ability to deal with various different configurations. In any event, in operation of all such systems, it is generally desirable to hold off the coming on line of the secondary processors until the primary processor configuration is established. Then it is desirable for the secondary processors to be brought up in an orderly fashion.
Although it would seem that the deficiencies and shortcomings of the proir art relating to powering up of a multiple processor system would have heretofore generated teachings in U.S. Patents, that does not seem to have been the case although a number of U.S. Patents have delth with the orderly powering up of peripheral units. For example, U.S. Pat. No. 4,593,349 to chase et al. discloses a peripheral power control sequencer incorporating a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The Chase et al. patent teaches time-sharing the terminals of the input/output ports of the microcomputer to accommodate the several input and output signals needed to accomplish the sequential powering of the peripheral control units. Another prior art patent dealing with peripheral units is U.S. Pat. No. 4,312,035 to Greene. The Greene patent discloses an apparatus for controlling electrical power in a data processing system having one or more central processing units and a plurality of peripheral units, including circuitry for selectively connecting a voltage signal to each peripheral unit to cause power to be supplied thereto. The apparatus taught in the Greene patent also includes metering means for measuring the amount of time the voltage signal is provided to each separate peripheral whereby the supply of power to any one of the peripheral units may be centrally monitored and controlled. Yet other U.S. patents in this general area are U.S. Pat. No. 4,809,163 to Hirosawa et al., U.S. Pat. No. 4,794,525 to Pickert et al. and U.S. Pat. No. 4,677,566 to Whittaker et al.
Based upon the foregoing, it is clear that the prior art has not been able, without being subject to stringent software dependant constraints, to allow multiple processors in a system to share resources and still maintain an orderly coordinated power on reset. Futhermore, the prior art has not produced a power on reset means which satisfies the needs of multiple processor/shared resources with respect to coordinated power on activities while still allowing great flexibility in the design of multiprocessor systems.